Marginal switching arrangement

ABSTRACT

The arrangement provides two long-tail transistor pairs with paralleled collector outputs and a detecting device branched across the above pair of outputs. The input signal is compared with the upper and lower levels of the selected range by means of the first and a second transistor pair and gives rise to equal potentials at both ends of the detecting device except when this input signal is above or below the range.

United States Patent Inventor Jean Victor Martens Deurne-Zuid, BelgiumAppl. No. 776,473 Filed Nov. 18, 1968 Patented July 13, 1971 AssigneeInternational Standard Electric Corporation New York, N.Y. Priority Dec.29, 1967 Belgium BL 29 MARGINAL SWITCHING ARRANGEMENT 7 Claims, 2Drawing Figs.

U.S. Cl 307/235, 3 1 7/1 48.5

Int. Cl H03k 5/20 Field of Search 307/235,

[56] References Cited UNITED STATES PATENTS 3,139,562 6/1964 Freeborn307/235 X 3,428,826 2/1969 Berry 307/235 3,470,497 9/1969 Kotter 307/235X Primary Examiner-Donald D. Forrer Assistant Exam iner-John ZazworskyAttorneys-C. Cornell Remsen, Jr., Walter J. Baum, Percy P. Lantzy,Philip M. Bolton, Isidore Otogut and Charles L. Johnson, Jr.

ABSTRACT: The arrangement provides two long-tail transistor pairs withparalleled collector outputs and a detecting device branched across theabove pair of outputs. The input signal is compared with the upper andlower levels of the selected range by means of the first and a secondtransistor pair and gives rise to equal potentials at both ends of thedetecting device except when this input signal is above or below therange.

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Q5 05 i 42 M 3 1 W iz/7 @g A Home y MARGINAL SWITCHING ARRANGEMENTBACKGROUND OF THE INVENTION The present invention relates to a marginalswitching arrangement for operating an output detecting device when theamplitude of the input signal lies outside a predetermined range.

Such a marginal switching arrangement is known from the Dutch patentapplication Ser. No. 250,589. This known-arrangement has a lowperformance, since its characteristics depend on temperature and supplyvoltage variations.

SUMMARY OF THE INVENTION An object of the present invention is toprovide an improved marginal switching arrangement of the above type,which does not present the mentioned drawbacks.

The present marginal switching arrangement is characterized by the fact,that said device is included in the branch of a 4-pole circuit having nocommon pole with a source of energy feeding said circuit which includesat least two branches whose impedances are jointly controlled by saidinput signals and two fixed reference sources defining said range sothat it acts as a substantially balanced bridge except when said inputsignals are above or below said range.

BRIEF DESCRIPTION OF THE DRAWINGS The abov: mentioned and other objectsand features of the invention will become more apparent and theinvention itself will be best understood by referring to the followingdescription of embodiments taken in conjunction with the accompanyingdrawings in which:

FIG. 1 shows a marginal switching arrangement in accordance with theinvention;

FIG. 2 shows a modification of a detecting device used in FIG. 1.

DESCRIPTION OF THE PREFERRED EMBODIMENTS Referring to FIG. 1 themarginal switching arrangement shown therein comprises two long-tailtransistor pairs .Q lQ and Q /Q The bases of transistors Q and Q areconnected in common and their junction point is connected to an outputof a signal source S via a resistor R The other output of signal sourceS is connected to ground.

The bases of transistors Q and Q are connected through respectiveresistors R, and R to the junction point of a resistor R and a Zenerdiode W forming potentiometer. The other end of resistor R and the anodeof diode W are respectively connected to a source V of positive DCpotential and to ground. The base of transistor Q is further connectedto ground via a resistor R The common connection points of the emittersof transistor pairs Q lQ and Q /Q, are connected to ground via aresistor R, and a resistor R (R /1R respectively. ResistorsR and'litsimulate constant current sources. The collectors of transistors Q and Q3 are connected together as are the collectors of transistors Q and Qand the respective junction points are connected to the source V viaresistors IR and R respectively; (R =R The junction points of thecollectors of transistors Q,Q and Q Q, are interconnected via a relayPr. The output of the arrangement, referred to as OUT, is taken across amake contact p of relay Pr.

The marginal switching arrangement of FIG. 2 is similar to thearrangement of FIG. 1, except that the output relay Pr and its contact pare replaced by a bistate circuit comprising the PNP transistors Q Q andQ The bases of transistors Q and Q; are connected to the junction pointsof the collectors of transistors Q,--Q and Q Q respectively. Theemitters of transistors Q and Q, are connected to each other and theirjunction point is connected to the source V via the emittercollectorjunction of the transistors Q which plays the role of a Zener diode. Thecollectors of transistors Q and Q are also connected to each other,their junction point being connected to ground via a resistor R Theoutput of the arrangement, referred to as OUT, is taken from theinterconnected collectors of transistor pair Q lQ The principle ofoperation of the marginal switching arrangement of FIG, 1 is as follows:

As long as the output voltage level of the source S, lies inside apredetermined range defined by the upper and lower reference voltages Mand m applied to the bases of transistors Q and Q respectively, relay Prremains in its nonenergized condition and consequently its make contactp remains open. Indeed, the constant currents i, and i feeding thelong-tail transistor pairs (),/Q and Q /Q circulate from the bias sourceV to ground via the resistors R, and R the collectoremitter junctions oftransistors Q and Q and the resistor R, and R respectively. Due to thevoltage drop across resistor R being equal to the voltage drop acrossresistor R (R =R i =i no current circulates through relay Pr so thatcontact 5 remains open. As soon as the output voltage level of signalsources becomes higher than the reference level M applied to the base oftransistor Q transistors Q and Q conduct, whereas transistors Q and Qare cut off. Alternatively, as soon as the output voltage level ofsignal source S becomes lower than the reference level m applied to thebase of transistor Q transistors Q and Q conduct, whereas transistors Q,and Q are cutoff. Assuming that the resistance of the winding of relayPr is very low with respect to the resistances R and R a current equalto current i or i 2 (i,=i circulates through relay Pr. Relay Pr is thusenergized and closes its contact p. The closure of contact p causes theactivation of an alarm circuit (not shown).

The marginal arrangement of FIG. 2 is adapted for being used inapplications where a high degree of accuracy is required or where highoperation speed requirements exclude the use of relay Pr. Thisarrangement provides a positive output voltage when the voltage appliedto its input by the signal source S is outside the range fixed by thelimits M and m. The operation of the arrangement of FIG. 2 is similar tothat of FIG. I as far as transistor pairs Q IQ and Q3/Q4 are concerned.The output bistate circuit comprising the transistors 5 to Q operates asfollows:

The total threshold voltage V of the latter circuit, constituted by theZener voltage of transistor Q plus the base-emitter voltage oftransistor Q, or Q, is higher than the voltage drop across resistor R orR when the voltage provided by source S is within the range fixed by thelimits M and m. In this condition neither transistor Q nor Q conducts;thus the output of the arrangement is at the ground potential.

When the voltage provided by source S is above or below the range fixedby the limits M and m, all the current from transistors Q, and Q or Qand Q tends to flow through only one of the resistors R or Rrespectively. The voltage drop across this one resistor R or R doublesand is higher than the aforementioned threshold voltage V Thecorresponding transistor Q or Q, is then conducting and the voltageacross resistor R jumps up to the emitter voltage of transistors Q and Iclaim:

I. A marginal switching circuit comprising:

a first transistor;

a second transistor, the emitter of which is coupled to the emitter ofsaid first transistor;

a third transistor, the collector of which is coupled to the collectorof said first transistor;

a fourth transistor, the emitter of which is coupled to the emitter ofsaid third transistor and the collector of which is coupled to thecollector of said second transistor;

means for providing a first reference voltage level to the base of saidsecond transistor;

means for providing a second reference voltage level, different thansaid first reference voltage level to the base of said fourthtransistor;

means for applying a third variable voltage level to the base of saidfirst and third transistors; and

means coupled between the collectors of said first and secondtransistors for responding when the level of said third voltage liesoutside the range bounded by said first and second reference voltagelevels.

2. A marginal switching circuit, according to claim 1, wherein saidresponsive means is a current energized relay.

3. A marginal switching circuit, according to claim 2, wherein saidfirst and third transistors conduct and said second and fourthtransistors are cut off when the level of said third variable voltageexceeds the range bounded by said first and second reference voltagelevels thereby providing a current flow through said relay.

4. A marginal switching circuit, according to claim 2, wherein saidsecond and fourth transistors conduct and said first and thirdtransistors are cut off when the level of said third variable voltage isbelow the range bounded by said first and second reference voltagelevels, thereby providing a current flow through said relay.

5. A marginal switching circuit, according to claim 1, wherein saidresponsive means comprises:

a fifth transistor, the base of which is coupled to the collector ofsaid first transistor;

a sixth transistor, the base of which is coupled to the collector of thesecond transistor, the emitters of said fifth and sixth transistorsbeing coupled one to the other, and the collectors of said fifth andsixth transistors being coupled one to the other; and

means for providing a fourth reference voltage level to the junction ofthe emitters of said fifth and sixth transistors.

6. A marginal switching circuit, according to claim 5, wherein saidfirst and third transistors conduct and said second and fourthtransistors are cut off when the level of said third voltage exceeds therange bounded by said first and second reference voltage levels, therebyproviding that said fifth transistor conducts and said sixth transistoris cut off.

7. A marginal switching circuit, according to claim 5, wherein saidsecond and fourth transistors conduct and said first and thirdtransistors are cut off when the level of said third voltage is belowthe range bounded by said first and second reference voltage levels,thereby providing that said sixth transistor conduct and said fifthtransistor is cut off.

1. A marginal switching circuit comprising: a first transistor; a secondtransistor, the emitter of which is coupled to the emitter of said firsttransistor; a third transistor, the collector of which is coupled to thecollector of said first transistor; a fourth transistor, the emitter ofwhich is coupled to the emitter of said third transistor and thecollector of which is coupled to the collector of said secondtransistor; means for providing a first reference voltage level to thebase of said second transistor; means for providing a second referencevoltage level, different than said first reference voltage level to thebase of said fourth transistor; means for applying a third variablevoltage level to the base of said first and third transistors; and meanscoupled between the collectors of said first and second transistors forresponding when the level of said third voltage lies outside the rangebounded by said first and second reference voltage levels.
 2. A marginalswitching circuit, according to claim 1, wherein said responsive meansis a current energized relay.
 3. A marginal switching circuit, accordingto claim 2, wherein said first and third transistors conduct and saidsecond and fourth transistors are cut off when the level of said thirdvariable voltage exceeds the range bounded by said first and secondreference voltage levels thereby providing a current flow through saidrelay.
 4. A marginal switching circuit, according to claim 2, whereinsaid second and fourth transistors conduct and said first and thirdtransistors are cut off when the level of said third variable voltage isbelow the range bounded by said first and second reference voltagelevels, thereby providing a current flow through said relay.
 5. Amarginal switching circuit, according to claim 1, wherein saidresponsive means compriSes: a fifth transistor, the base of which iscoupled to the collector of said first transistor; a sixth transistor,the base of which is coupled to the collector of the second transistor,the emitters of said fifth and sixth transistors being coupled one tothe other, and the collectors of said fifth and sixth transistors beingcoupled one to the other; and means for providing a fourth referencevoltage level to the junction of the emitters of said fifth and sixthtransistors.
 6. A marginal switching circuit, according to claim 5,wherein said first and third transistors conduct and said second andfourth transistors are cut off when the level of said third voltageexceeds the range bounded by said first and second reference voltagelevels, thereby providing that said fifth transistor conducts and saidsixth transistor is cut off.
 7. A marginal switching circuit, accordingto claim 5, wherein said second and fourth transistors conduct and saidfirst and third transistors are cut off when the level of said thirdvoltage is below the range bounded by said first and second referencevoltage levels, thereby providing that said sixth transistor conduct andsaid fifth transistor is cut off.